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ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 1 69921234fc typical a pplica t ion descrip t ion timerblox: voltage-controlled pulse width modulator (pwm) the ltc ? 6992 is a silicon oscillator with an easy-to-use analog voltage-controlled pulse width modulation (pwm) capability. the ltc6992 is part of the timerblox ? family of versatile silicon timing devices. a single resistor, r set , programs the ltc6992s inter - nal master oscillator frequency. the output frequency is determined by this master oscillator and an internal frequency divider, n div , programmable to eight settings from 1 to 16384. f out = 1mhz n div ? 50k r set , n div = 1,4,16 ?16384 applying a voltage between 0v and 1v on the mod pin sets the duty cycle. the four versions differ in their minimum/maximum duty cycle. note that a minimum duty cycle limit of 0% or maximum duty cycle limit of 100% allows oscillations to stop at the extreme duty cycle settings. device name pwm duty cycle range ltc6992-1 0% to 100% ltc6992-2 5% to 95% ltc6992-3 0% to 95% ltc6992-4 5% to 100% fo r easy configuration of the ltc6992, download the timerblox designer tool at www.linear.com/timerblox . n pulse width modulation (pwm) controlled by simple 0v to 1v analog input n four available options define duty cycle limits C minimum duty cycle at 0% or 5% C maximum duty cycle at 95% or 100% n frequency range: 3.81hz to 1mhz n configured with 1 to 3 resistors n <1.7% maximum frequency error n pwm duty cycle error < 3.7% maximum n frequency modulation (vco) capability n 2.25v to 5.5v single supply operation n 115a supply current at 100khz n 500s start-up time n cmos output driver sources/sinks 20ma n C55c to 125c operating temperature range n available in low profile (1mm) sot-23 (thinsot?) and 2mm 3mm dfn l , lt, ltc and ltm, linear technology, timerblox and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. fea t ures a pplica t ions n pwm servo loops n heater control n led dimming control n high vibration, high acceleration environments n portable and battery-powered equipment 6992 ta01a ltc6992 mod gnd set out v + div r set 50k 3.3v analog pwm duty cycle control (0v to 1v) c1 0.1f 1mhz pulse width modulator mod 0.5v/div out 1v/div 2s/div 6992 ta01b
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 2 69921234fc a bsolu t e maxi m u m r a t ings supply voltage (v + ) to gnd ......... . 6v maximum voltage on any pin ............................. ( gnd C 0.3v) v pin (v + + 0.3v) operating temperature range (note 2) ltc6992c ............................................ C 40c to 85c ltc6992i ............................................. C 40c to 85c ltc6992h .......................................... C4 0c to 125c ltc6992mp ....................................... C 55c to 125c (note 1) top view out gnd mod v+ div set dcb package 6-lead (2mm 3mm) plastic dfn 4 5 7 gnd 6 3 2 1 t jmax = 150c, ja = 64c/w, jc = 10.6c/w exposed pad (pin 7) is gnd, pcb connection is optional mod 1 gnd 2 set 3 6 out 5 v + 4 div top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 192c/w, jc = 51c/w p in c on f igura t ion o r d er i n f or m a t ion specified temperature range (note 3) ltc6992c ................................................ 0 c to 70c ltc6992i ............................................. C 40c to 85c ltc6992h .......................................... C4 0c to 125c ltc6992mp ....................................... C 55c to 125c junction temperature .......................................... 15 0c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) s6 package ....................................................... 3 00c lead free finish tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6992cdcb-1#trmpbf ltc6992cdcb-1#trpbf ldxc 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6992idcb-1#trmpbf ltc6992idcb-1#trpbf ldxc 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6992hdcb-1#trmpbf ltc6992hdcb-1#trpbf ldxc 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6992cs6-1#trmpbf ltc6992cs6-1#trpbf ltdxb 6-lead plastic tsot-23 0c to 70c ltc6992is6-1#trmpbf ltc6992is6-1#trpbf ltdxb 6-lead plastic tsot-23 C40c to 85c ltc6992hs6-1#trmpbf ltc6992hs6-1#trpbf ltdxb 6-lead plastic tsot-23 C40c to 125c ltc6992cdcb-2#trmpbf ltc6992cdcb-2#trpbf ldxf 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6992idcb-2#trmpbf ltc6992idcb-2#trpbf ldxf 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6992hdcb-2#trmpbf ltc6992hdcb-2#trpbf ldxf 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6992cs6-2#trmpbf ltc6992cs6-2#trpbf ltdxd 6-lead plastic tsot-23 0c to 70c ltc6992is6-2#trmpbf ltc6992is6-2#trpbf ltdxd 6-lead plastic tsot-23 C40c to 85c ltc6992hs6-2#trmpbf ltc6992hs6-2#trpbf ltdxd 6-lead plastic tsot-23 C40c to 125c ltc6992cdcb-3#trmpbf ltc6992cdcb-3#trpbf lfcp 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6992idcb-3#trmpbf ltc6992idcb-3#trpbf lfcp 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6992hdcb-3#trmpbf ltc6992hdcb-3#trpbf lfcp 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6992cs6-3#trmpbf ltc6992cs6-3#trpbf ltfcq 6-lead plastic tsot-23 0c to 70c ltc6992is6-3#trmpbf ltc6992is6-3#trpbf ltfcq 6-lead plastic tsot-23 C40c to 85c ltc6992hs6-3#trmpbf ltc6992hs6-3#trpbf ltfcq 6-lead plastic tsot-23 C40c to 125c
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 3 69921234fc or d er in f or m a t ion the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, v mod = 0v to v set , divcode = 0 to 15 (n div = 1 to 16,384), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted. e lec t rical c harac t eris t ics symbol parameter conditions min typ max units oscillation frequency f out output frequency 3.81 1000000 hz ?f out frequency accuracy (note 4) 3.81hz f out 1mhz l 0.8 1.7 2.4 % % ?f out /?t frequency drift over temperature l 0.005 %/c ?f out /?v + frequency drift over supply v + = 4.5v to 5.5v v + = 2.25v to 4.5v l l 0.25 0.08 0.65 0.18 %/v %/v long-term frequency stability (note 10) 90 ppm/khr period jitter (note 9) n div = 1 1.2 % p-p n div = 4 0.4 0.07 % p-p % rms n div = 16 0.15 0.022 % p-p % rms pulse width modulation ?d pwm duty cycle accuracy v mod = 0.2 ? v set to 0.8 ? v set v mod = 0.2 ? v set to 0.8 ? v set v mod < 0.2 ? v set or v mod > 0.8 ? v set l l 3.0 3.7 4.5 4.9 % % % d max maximum duty cycle limit ltc6992-1/ltc6992-4, pol = 0, v mod = 1v l 100 % ltc6992-2/ltc6992-3, pol = 0, v mod = 1v l 90.5 95 99 % d min minimum duty cycle limit ltc6992-1/ltc6992-3, pol = 0, v mod = 0v l 0 % ltc6992-2/ltc6992-4, pol = 0, v mod = 0v l 1 5 9.5 % t s,pwm duty cycle settling time (note 6) t master = t out /n div 8?t master s lead free finish tape and reel (mini) tape and reel part marking* package description specified temperature range ltc6992cdcb-4#trmpbf ltc6992cdcb-4#trpbf lfcr 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6992idcb-4#trmpbf ltc6992idcb-4#trpbf lfcr 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6992hdcb-4#trmpbf ltc6992hdcb-4#trpbf lfcr 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6992cs6-4#trmpbf ltc6992cs6-4#trpbf ltfcs 6-lead plastic tsot-23 0c to 70c ltc6992is6-4#trmpbf ltc6992is6-4#trpbf ltfcs 6-lead plastic tsot-23 C40c to 85c ltc6992hs6-4#trmpbf ltc6992hs6-4#trpbf ltfcs 6-lead plastic tsot-23 C40c to 125c ltc6992mps6-1#trmpbf ltc6992mps6-1#trpbf ltdxb 6-lead plastic tsot-23 C55c to 125c ltc6992mps6-2#trmpbf ltc6992mps6-2#trpbf ltdxd 6-lead plastic tsot-23 C55c to 125c ltc6992mps6-3#trmpbf ltc6992mps6-3#trpbf ltfcq 6-lead plastic tsot-23 C55c to 125c ltc6992mps6-4#trmpbf ltc6992mps6-4#trpbf ltfcs 6-lead plastic tsot-23 C55c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 4 69921234fc the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, v mod = 0v to v set , divcode = 0 to 15 (n div = 1 to 16,384), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted. e lec t rical c harac t eris t ics symbol parameter conditions min typ max units power supply v + operating supply voltage range l 2.25 5.5 v power-on reset voltage l 1.95 v i s supply current r l = , r set = 50k, n div = 1 v + = 5.5v l 365 450 a v + = 2.25v l 225 285 a r l = , r set = 50k, n div = 4 v + = 5.5v l 350 420 a v + = 2.25v l 225 280 a r l = , r set = 50k, n div 16 v + = 5.5v l 325 390 a v + = 2.25v l 215 265 a r l = , r set = 800k, n div = 1 to 16,384 v + = 5.5v l 120 170 a v + = 2.25v l 105 150 a analog inputs v set voltage at set pin l 0.97 1.00 1.03 v ?v set /?t v set drift over temperature l 75 v/c r set frequency-setting resistor l 50 800 k mod pin input capacitance 2.5 pf mod pin input current l 10 na v mod,hi v mod voltage for maximum duty cycle ltc6992-1/ltc6992-4, pol = 0, d = 100% ltc6992-2/ltc6992-3, pol = 0, d = 95% l 0.90 ? v set 0.86 ? v set 0.936 ? v set v v v mod,lo v mod voltage for minimum duty cycle ltc6992-1/ltc6992-3, pol = 0, d = 0% ltc6992-2/ltc6992-4, pol = 0, d = 5% l 0.064 ? v set 0.10 ? v set 0.14 ? v set v v v div div pin voltage l 0 v + v ?v div /?v + div pin valid code range (note 5) deviation from ideal v div /v + = (divcode + 0.5)/16 l 1.5 % div pin input current l 10na digital output i out(max) output current v + = 2.7v to 5.5v 20 ma v oh high level output voltage (note 7) v + = 5.5v i out = C1ma i out = C16ma l l 5.45 4.84 5.48 5.15 v v v + = 3.3v i out = C1ma i out = C10ma l l 3.24 2.75 3.27 2.99 v v v + = 2.25v i out = C1ma i out = -8ma l l 2.17 1.58 2.21 1.88 v v v ol low level output voltage (note 7) v + = 5.5v i out = 1ma i out = 16ma l l 0.02 0.26 0.04 0.54 v v v + = 3.3v i out = 1ma i out = 10ma l l 0.03 0.22 0.05 0.46 v v v + = 2.25v i out = 1ma i out = 8ma l l 0.03 0.26 0.07 0.54 v v t r output rise time (note 8) v + = 5.5v, r load = v + = 3.3v, r load = v + = 2.25v, r load = 1.1 1.7 2.7 ns ns ns t f output fall time (note 8) v + = 5.5v, r load = v + = 3.3v, r load = v + = 2.25v, r load = 1.0 1.6 2.4 ns ns ns
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 5 69921234fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6992c is guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6992c is guaranteed to meet specified performance from 0c to 70c. the ltc6992c is designed, characterized and expected to meet specified performance from C40c to 85c but it is not tested or qa sampled at these temperatures. the ltc6992i is guaranteed to meet specified performance from C40c to 85c. the ltc6992h is guaranteed to meet specified performance from C40c to 125c. the ltc6992mp is guaranteed to meet specified performance from C55c to 125c. note 4: frequency accuracy is defined as the deviation from the f out equation, assuming r set is used to program the frequency. note 5: see operation section, table 1 and figure 2 for a full explanation of how the div pin voltage selects the value of divcode. note 6: duty cycle settling time is the amount of time required for the output to settle within 1% of the final duty cycle after a 10% change in the setting (80mv step in v mod ). note 7: to conform to the logic ic standard, current out of a pin is arbitrarily given a negative value. note 8: output rise and fall times are measured between the 10% and the 90% power supply levels with 5pf output load. these specifications are based on characterization. note 9: jitter is the ratio of the peak-to-peak deviation of the period to the mean of the period. this specification is based on characterization and is not 100% tested. note 10: long-term drift of silicon oscillators is primarily due to the movement of ions and impurities within the silicon and is tested at 30c under otherwise nominal operating conditions. long-term drift is specified as ppm/khr due to the typically nonlinear nature of the drift. to calculate drift for a set time period, translate that time into thousands of hours, take the square root and multiply by the typical drift number. for instance, a year is 8.77khr and would yield a drift of 266ppm at 90ppm/khr. drift without power applied to the device may be approximated as 1/10th of the drift with power, or 9ppm/ khr for a 90ppm/khr device. e lec t rical c harac t eris t ics typical p er f or m ance c harac t eris t ics frequency error vs temperature frequency error vs temperature frequency error vs temperature v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted. temperature (c) ?50 ?3 0 1 2 3 0 25 50 100 125 ?1 ?2 ?25 75 6992 g01 error (%) r set = 50k 3 parts guaranteed max over temperature guaranteed min over temperature temperature (c) ?50 ?3 0 1 2 3 0 25 50 100 125 ?1 ?2 ?25 75 6992 g02 error (%) r set = 200k 3 parts guaranteed max over temperature guaranteed min over temperature temperature (c) ?50 ?3 0 1 2 3 0 25 50 100 125 ?1 ?2 ?25 75 6992 g03 error (%) r set = 800k 3 parts guaranteed max over temperature guaranteed min over temperature
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 6 69921234fc frequency error vs r set frequency drift vs supply voltage typical v set distribution v set drift vs i set v set drift vs supply v set vs temperature r set (k) 50 ?3 0 1 2 3 200 400 800 ?1 ?2 100 6992 g04 error (%) 3 parts guaranteed max over temperature guaranteed min over temperature supply voltage (v) 2 ?0.5 0 0.2 0.1 0.3 0.4 0.5 4 5 6 ?0.2 ?0.1 ?0.3 ?0.4 3 6992 g05 drift (%) referenced to v + = 4.5v r set = 50k r set = 200k r set = 800k v set (v) 0.98 0 100 50 150 200 250 0.996 1.004 1.012 1.02 0.988 6992 g06 number of units 2 lots dfn and sot-23 1274 units i set (a) 0 ?1.0 0 0.4 0.2 0.6 0.8 1.0 10 15 20 ?0.4 ?0.2 ?0.6 ?0.8 5 6992 g07 v set (mv) referenced to i set = 10a supply (v) 2 ?1.0 0 0.4 0.2 0.6 0.8 1.0 4 5 6 ?0.4 ?0.2 ?0.6 ?0.8 3 6992 g08 drift (mv) referenced to v + = 4v temperature (c) ?50 0.980 1.000 1.010 1.005 1.015 1.020 0 25 50 100 125 0.995 0.990 0.985 ?25 75 6992 g09 v set (v) 3 parts n div = 1 duty cycle error vs r set n div = 1 duty cycle error vs r set n div = 1 duty cycle error vs r set r set (k) 50 ?5 0 3 2 1 4 5 100 400 800 ?1 ?2 ?3 ?4 200 6992 g10 error (%) v mod /v set = 0.2 (12.5%) divcode = 0 3 parts r set (k) 50 ?5 0 3 2 1 4 5 100 400 800 ?1 ?2 ?3 ?4 200 6992 g11 error (%) v mod /v set = 0.5 (50%) divcode = 0 3 parts r set (k) 50 ?5 0 3 2 1 4 5 100 400 800 ?1 ?2 ?3 ?4 200 6992 g12 error (%) v mod /v set = 0.8 (87.5%) divcode = 0 3 parts typical p er f or m ance c harac t eris t ics v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted.
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 7 69921234fc typical p er f or m ance c harac t eris t ics n div > 1 duty cycle error vs r set n div > 1 duty cycle error vs r set n div > 1 duty cycle error vs r set n div = 1 duty cycle clamps vs r set n div > 1 duty cycle error vs r set r set (k) 50 ?5 0 3 2 1 4 5 100 400 800 ?1 ?2 ?3 ?4 200 6992 g13 error (%) v mod /v set = 0.2 (12.5%) divcode = 4 3 parts r set (k) 50 ?5 0 3 2 1 4 5 100 400 800 ?1 ?2 ?3 ?4 200 6992 g14 error (%) v mod /v set = 0.5 (50%) divcode = 4 3 parts r set (k) 50 ?5 0 3 2 1 4 5 100 400 800 ?1 ?2 ?3 ?4 200 6992 g15 error (%) v mod /v set = 0.8 (87.5%) divcode = 4 3 parts r set (k) 50 3 8 95 94 93 92 96 97 100 400 800 7 6 5 4 200 6992 g16 error (%) divcode = 0 3 parts ltc6992-2/ltc6992-3 v mod = v set ltc6992-2/ltc6992-4 v mod = v set r set (k) 50 3 8 95 94 93 92 96 97 100 400 800 7 6 5 4 200 6992 g17 error (%) divcode = 4 3 parts ltc6992-2/ltc6992-3 v mod = v set ltc6992-2/ltc6992-4 v mod = v set v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted. n div = 1 duty cycle error vs temperature temperature (c) ?50 ?5 0 1 2 3 4 5 0 25 50 100 125 ?1 ?2 ?3 ?4 ?25 75 6992 g18 error (%) v mod /v set = 0.2 (12.5%) divcode = 0 3 parts guaranteed max guaranteed min n div = 1 duty cycle error vs temperature temperature (c) ?50 ?5 0 1 2 3 4 5 0 25 50 100 125 ?1 ?2 ?3 ?4 ?25 75 6992 g19 error (%) v mod /v set = 0.5 (50%) divcode = 0 3 parts guaranteed max guaranteed min n div = 1 duty cycle error vs temperature temperature (c) ?5 0 1 2 3 4 5 ?1 ?2 ?3 ?4 6992 g20 error (%) v mod /v set = 0.8 (87.5%) divcode = 0 3 parts guaranteed max guaranteed min ?50 0 25 50 100 125 ?25 75 n div > 1 duty cycle error vs temperature temperature (c) ?50 ?5 0 1 2 3 4 5 0 25 50 100 125 ?1 ?2 ?3 ?4 ?25 75 6992 g21 error (%) v mod /v set = 0.2 (12.5%) divcode = 4 3 parts guaranteed max guaranteed min
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 8 69921234fc typical p er f or m ance c harac t eris t ics n div > 1 duty cycle error vs temperature n div > 1 duty cycle error vs temperature n div = 1 duty cycle clamps vs temperature n div > 1 duty cycle clamps vs temperature temperature (c) ?50 ?5 0 1 2 3 4 5 0 25 50 100 125 ?1 ?2 ?3 ?4 ?25 75 6992 g22 error (%) v mod /v set = 0.5 (50%) divcode = 4 3 parts guaranteed max guaranteed min temperature (c) ?50 ?5 0 1 2 3 4 5 0 25 50 100 125 ?1 ?2 ?3 ?4 ?25 75 6992 g23 error (%) v mod /v set = 0.8 (87.5%) divcode = 4 3 parts guaranteed max guaranteed min temperature (c) ?50 ?25 3 8 95 94 93 92 96 97 50250 100 125 7 6 5 4 75 6992 g24 error (%) divcode = 0 3 parts ltc6992-2/ltc6992-3 v mod = v set ltc6992-2/ltc6992-4 v mod = gnd temperature (c) ?50 ?25 3 8 95 94 93 92 96 97 50250 100 125 7 6 5 4 75 6992 g25 duty cycle (%) divcode = 4 3 parts ltc6992-2/ltc6992-3 v mod = v set ltc6992-2/ltc6992-4 v mod = gnd v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted. n div = 1 duty cycle vs v mod / v set n div > 1 duty cycle vs v mod / v set duty cycle error vs divcode duty cycle error vs divcode duty cycle error vs divcode v mod /v set (v/v) 0 0.2 0 40 80 70 60 50 90 100 0.8 0.6 0.4 1 30 20 10 6992 g29 duty cycle (%) divcode = 0 3 parts ltc6992-1/ ltc6992-4 ltc6992-2/ ltc6992-4 ltc6992-1/ltc6992-3 ltc6992-2/ ltc6992-3 v mod /v set (v/v) 0 0.2 0 40 80 70 60 50 90 100 0.8 0.6 0.4 1 30 20 10 6992 g30 duty cycle (%) divcode = 4 3 parts ltc6992-1/ ltc6992-4 ltc6992-2/ ltc6992-4 ltc6992-1/ltc6992-3 ltc6992-2/ ltc6992-3 divcode 0 2 ?5 ?1 3 2 1 0 4 5 864 12 14 ?2 ?3 ?4 10 6992 g26 error (%) v mod / v set = 0.2 (12.5%) 3 parts divcode 0 2 ?5 ?1 3 2 1 0 4 5 864 12 14 ?2 ?3 ?4 10 6992 g27 error (%) v mod / v set = 0.5 (50%) 3 parts divcode 0 2 ?5 ?1 3 2 1 0 4 5 864 12 14 ?2 ?3 ?4 10 6992 g28 error (%) v mod / v set = 0.8 (87.5%) 3 parts
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 9 69921234fc typical p er f or m ance c harac t eris t ics n div > 1 duty cycle vs v mod / v set n div = 1 duty cycle error vs ideal n div > 1 duty cycle error vs ideal n div > 1 duty cycle error vs ideal v mod /v set (v/v) 0 0.2 0 40 80 70 60 50 90 100 0.8 0.6 0.4 1 30 20 10 6992 g31 duty cycle (%) divcode = 11 3 parts ltc6992-1/ ltc6992-4 ltc6992-2/ ltc6992-4 ltc6992-1/ltc6992-3 ltc6992-2/ ltc6992-3 ideal duty cycle (%) ?5 0 4 3 2 1 5 50250 100 ?1 ?2 ?3 ?4 75 6992 g32 error (%) divcode = 0 3 parts part a part b part c ideal duty cycle (%) ?5 0 4 3 2 1 5 50250 100 ?1 ?2 ?3 ?4 75 6992 g33 error (%) divcode = 4 3 parts part a part b part c ideal duty cycle (%) ?5 0 4 3 2 1 5 50250 100 ?1 ?2 ?3 ?4 75 6992 g34 error (%) divcode = 11 3 parts part a part b part c v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted. linearity near 100% duty cycle v mod /v set (v/v) 88 95 99 98 97 96 100 0.836 0.804 0.9 94 93 92 91 90 89 0.868 6992 g35 duty cycle (%) divcode = 4 ltc6992-1/ltc6992-4 3 parts linearity near 95% duty cycle v mod /v set (v/v) 88 95 99 98 97 96 100 0.836 0.804 0.9 94 93 92 91 90 89 0.868 6992 g36 duty cycle (%) divcode = 4 ltc6992-2/ltc6992-3 3 parts linearity near 67% duty cycle v mod /v set (v/v) 62 67 71 70 69 68 72 0.612 0.628 0.644 0.596 0.676 66 65 64 63 0.66 6992 g37 duty cycle (%) divcode = 4 3 parts linearity near 0% duty cycle v mod /v set (v/v) 0 7 11 10 9 8 12 0.116 0.148 0.084 0.18 6 5 4 3 2 1 6992 g38 duty cycle (%) divcode = 4 ltc6992-1/ltc6992-3 3 parts linearity near 5% duty cycle v mod /v set (v/v) 0 7 11 10 9 8 12 0.116 0.148 0.084 0.18 6 5 4 3 2 1 6992 g39 duty cycle (%) divcode = 4 ltc6992-2/ltc6992-4 3 parts
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 10 69921234fc typical p er f or m ance c harac t eris t ics linearity near 31% duty cycle n div = 1 duty cycle drift vs supply n div > 1 duty cycle drift vs supply supply current vs v mod v mod /v set (v/v) 26 31 35 34 33 32 36 0.324 0.34 0.356 0.372 0.308 0.388 30 29 28 27 6992 g40 duty cycle (%) divcode = 4 3 parts supply (v) ?0.5 0 0.4 0.3 0.2 0.1 0.5 3 4 5 2 6 ?0.1 ?0.2 ?0.3 ?0.4 6992 g41 drift (%) divcode = 0 v mod /v set = 0.5 v mod /v set = 0.2 v mod /v set = 0.8 5% clamp 95% clamp referenced to v + = 4v supply (v) ?0.5 0 0.4 0.3 0.2 0.1 0.5 3 4 5 2 6 ?0.1 ?0.2 ?0.3 ?0.4 6992 g42 drift (%) divcode = 4 referenced to v + = 4v v mod /v set = 0.5 v mod /v set = 0.2 v mod /v set = 0.8 5% clamp 95% clamp v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted. v mod (v) 0 250 350 300 400 0.4 0.2 0.6 0.8 0 1 200 150 100 50 6992 g43 power supply current (a) ltc6992-2 r set = 50k, 1 r set = 50k, 16 r set = 100k, 4 r set = 800k, 1 supply current vs frequency, 5v supply current vs frequency, 2.5v supply current vs supply voltage supply current vs temperature jitter vs frequency supply voltage (v) 0 250 350 300 400 3 4 5 2 6 200 150 100 50 6992 g44 power supply current (a) r set = 50k, 1 r set = 50k, 4 r set = 50k, 16 r set = 100k, 1 r set = 800k, 1 temperature (c) ?50 0 250 300 350 400 0 25 50 100 125 200 150 100 50 ?25 75 6992 g45 power supply current (a) 5.0v, r set = 50k, 1 2.5v, r set = 50k, 1 5.0v, r set = 50k, 16 5.0v, r set = 800k, 1 2.5v, r set = 800k, 1 frequency (khz) 0.01 0 1.4 1.6 1.8 2.0 0.1 1 100 1000 1.2 1.0 0.8 0.6 0.4 0.2 10 6992 g46 jitter (% p-p ) 1, v + = 5v 1, v + = 2.5v 4, v + = 5v 4, v + = 2.5v 16 64 peak-to-peak period deviation measured over 30s intervals v mod /v set = 0.5 frequency (khz) 0.001 0 250 300 350 400 0.10.01 1 100 1000 200 150 100 50 10 6992 g47 power supply current (a) 4 1 16,384 v + = 5v frequency (khz) 0.001 0 250 300 350 400 0.10.01 1 100 1000 200 150 100 50 10 6992 g48 power supply current (a) 4 1 16,384 v + = 2.5v
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 11 69921234fc typical p er f or m ance c harac t eris t ics output resistance vs supply voltage rise and fall time vs supply voltage typical i set current limit vs v + supply voltage (v) rise/fall time (ns) 6992 g51 3.0 1.5 2.5 1.0 0.5 2.0 0 2 4 3 5 6 c load = 5pf t rise t fall supply voltage (v) output resistance () 6992 g50 50 25 20 35 45 5 10 15 30 40 0 2 4 3 5 6 output sourcing current output sinking current supply voltage (v) i set (a) 6992 g52 1000 400 800 200 600 0 2 4 3 5 6 set pin shorted to gnd v + = 3.3v, r set = 200k, and t a = 25c, unless otherwise noted. typical start-up, pol = 0 typical start-up, pol = 1 v + 1v/div out 1v/div v + = 2.5v divcode = 3 (64) r set = 50k v mod = 0.3v (~25% duty cycle) 100s/div 6992 g53 500s v + 1v/div out 1v/div v + = 2.5v divcode = 12 (64, pol = 1) r set = 50k v mod = 0.2v (~87.5% duty cycle) 100s/div 6992 g54 500s 125khz full modulation v mod 0.5v/div out 1v/div v + = 3.3v divcode = 1 r set = 100k 50s/div 6992 g55 ltc6992-1 typical frequency error vs time (long-term drift) time (h) delta frequency (ppm) 6992 g48a 50 0 150 ?150 ?100 ?50 100 200 ?200 0 1200 400 800 1600 2000 2400 2800 65 units sot-23 and dfn parts t a = 30c
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 12 69921234fc p in func t ions v + (pin 1/pin 5): supply voltage (2.25v to 5.5v). this sup- ply should be kept free from noise and ripple. it should be bypassed directly to the gnd pin with a 0.1f capacitor. div (pin 2/pin 4): programmable divider and polarity input. the div pin voltage (v div ) is internally converted into a 4-bit result (divcode). v div may be generated by a resistor divider between v + and gnd. use 1% resistors to ensure an accurate result. the div pin and resistors should be shielded from the out pin or any other traces that have fast edges. limit the capacitance on the div pin to less than 100pf so that v div settles quickly. the msb of divcode (pol) determines if the pwm signal is inverted before driving the output. when pol = 1 the transfer func- tion is inverted (duty cycle decreasing as v mod increases). set (pin 3/pin 3): frequency-setting input. the voltage on the set pin (v set ) is regulated to 1v above gnd. the amount of current sourced from the set pin (i set ) pro- grams the master oscillator frequency. the i set current range is 1.25a to 20a. the output oscillation will stop if i set drops below approximately 500na. a resistor con- nected between set and gnd is the most accurate way to set the frequency. for best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/c or better temperature coefficient. for lower ac- curacy applications an inexpensive 1% thick film resistor may be used. limit the capacitance on the set pin to less than 10pf to minimize jitter and ensure stability. capacitance less than 100pf maintains the stability of the feedback circuit regulating the v set voltage. (dcb/s6) 6992 pf ltc6992 mod gnd set out v + div c1 0.1f r set r2 r1 v + v + mod (pin 4/pin 1): pulse-width modulation input. the voltage on the mod pin controls the output duty cycle. the linear control range is between 0.1 ? v set and 0.9 ? v set (approximately 100mv to 900mv). beyond those limits, the output will either clamp at 5% or 95%, or stop oscil- lating (0% or 100% duty cycle), depending on the version. gnd (pin 5/pin 2): ground. tie to a low inductance ground plane for best performance. out (pin 6/pin 6): oscillator output. the out pin swings from gnd to v + with an output resistance of approximately 30. the duty cycle is determined by the voltage on the mod pin. when driving an led or other low-impedance load a series output resistor should be used to limit the source/sink current to 20ma.
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 13 69921234fc b lock diagra m (s6 package pin numbers shown) 6992 bd programmable divider 1, 4, 16, 64, 256, 1024, 4096, 16384 master oscillator disable output until settled por output polarity digital filter 4-bit a/d converter f osc = 1mhz ? 50k ? i set v set pol r1 r2 div v + out d = t on t out 5 4 1 6 halt oscillator if i set < 500na mclk + ? i set v set = 1v + ? v ref 1v 3 22 gnd set mod r set duty cycle = v mod(lim) ? 0.1 ? v set 0.8 ? v set voltage limiter v mod(lim) v mod pulse width modulator t out t on
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 14 69921234fc o pera t ion the ltc6992 is built around a master oscillator with a 1mhz maximum frequency. the oscillator is controlled by the set pin current (i set ) and voltage (v set ), with a 1mhz ? 50k conversion factor that is accurate to 0.8% under typical conditions. f master = 1 t master = 1mhz s 50k s i set v set a feedback loop maintains v set at 1v 30mv, leaving i set as the primary means of controlling the output frequency. the simplest way to generate i set is to connect a resistor (r set ) between set and gnd, such that i set = v set /r set . the master oscillator equation reduces to: f master = 1 t master = 1mhz s 50k r set from this equation, it is clear that v set drift will not affect the output frequency when using a single program resistor (r set ). error sources are limited to r set tolerance and the inherent frequency accuracy ? f out of the ltc6992. r set may range from 50k to 800k (equivalent to i set between 1.25a and 20a). the ltc6992 includes a programmable frequency divider which can further divide the frequency by 1, 4, 16, 64, 256, 1024, 4096 or 16384 before driving the out pin. the divider ratio n div is set by a resistor divider attached to the div pin. f out = 1 t out = 1mhz s 50k n div s i set v set with r set in place of v set /i set the equation reduces to: f out = 1 t out = 1mhz s 50k n div s r set divcode the div pin connects to an internal, v + referenced 4-bit a/d converter that determines the divcode value. divcode programs two settings on the ltc6992: 1. divcode determines the output frequency divider set- ting, n div . 2. divcode determines the output polarity, via the pol bit. v div may be generated by a resistor divider between v + and gnd as shown in figure 1. figure 1. simple technique for setting divcode 6992 f01 ltc6992 v + div gnd r1 r2 2.25v to 5.5v
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 15 69921234fc table 1 offers recommended 1% resistor values that ac - curately produce the correct voltage division as well as the corresponding n div and pol values for the recommended resistor pairs. other values may be used as long as: 1. the v div /v + ratio is accurate to 1.5% (including resis- tor tolerances and temperature effects). 2. the driving impedance (r1||r2) does not exceed 500k. if the voltage is generated by other means (i.e. the output of a dac) it must track the v + supply voltage. the last column in table 1 shows the ideal ratio of v div to the supply voltage, which can also be calculated as: v div v + = divcode + 0.5 16 1.5% for example, if the supply is 3.3v and the desired divcode is 4, v div = 0.281 ? 3.3v = 928mv 50mv. figure 2 illustrates the information in table 1, showing that n div is symmetric around the divcode midpoint. table 1. divcode programming divcode pol n div recommended f out r1 (k) r2 (k) v div /v + 0 0 1 62.5khz to 1mhz open short 0.03125 0.015 1 0 4 15.63khz to 250khz 976 102 0.09375 0.015 2 0 16 3.906khz to 62.5khz 976 182 0.15625 0.015 3 0 64 976.6hz to 15.63khz 1000 280 0.21875 0.015 4 0 256 244.1hz to 3.906khz 1000 392 0.28125 0.015 5 0 1024 61.04hz to 976.6hz 1000 523 0.34375 0.015 6 0 4096 15.26hz to 244.1hz 1000 681 0.40625 0.015 7 0 16384 3.815hz to 61.04hz 1000 887 0.46875 0.015 8 1 16384 3.815hz to 61.04hz 887 1000 0.53125 0.015 9 1 4096 15.26hz to 244.1hz 681 1000 0.59375 0.015 10 1 1024 61.04hz to 976.6hz 523 1000 0.65625 0.015 11 1 256 244.1hz to 3.906khz 392 1000 0.71875 0.015 12 1 64 976.6hz to 15.63khz 280 1000 0.78125 0.015 13 1 16 3.906khz to 62.5khz 182 976 0.84375 0.015 14 1 4 15.63khz to 250khz 102 976 0.90625 0.015 15 1 1 62.5khz to 1mhz short open 0.96875 0.015 o pera t ion figure 2. frequency range and pol bit vs divcode 0.5 ? v + f out (khz) 6992 f02 1000 100 10 1 0.001 0.1 0.01 increasing v div v + 0v pol bit = 0 pol bit = 1 0 15 1 3 2 5 4 7 6 9 8 11 10 13 12 14
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 16 69921234fc pulse width (duty cycle) modulation the mod pin is a high impedance analog input providing direct control of the output duty cycle. the duty cycle is proportional to the voltage applied to the mod pin, v mod . duty cycle = d = v mod 0.8 ? v set ? 1 8 the pwm duty cycle accuracy ? d specifies that the above equation is valid to within 4.5% for v mod between 0.2 ? v set and 0.8 ? v set (12.5% to 87.5% duty cycle). since v set = 1v 30mv, the duty cycle equation may be approximated by the following equation. duty cycle = d ? v mod ? 100mv 800mv the v mod control range is approximately 0.1v to 0.9v. driving v mod beyond that range (towards gnd or v + ) will have no further affect on the duty cycle. duty cycle limits the only difference between the four versions of the ltc6992 is the limits, or clamps, placed on the output duty cycle. the ltc6992-1 generates output duty cycles ranging from 0% to 100%. at 0% or 100% the output will stop oscillating and rest at gnd or v + , respectively. the ltc6992-2 will never stop oscillating, regardless of the v mod level. internal clamping circuits limit its duty cycle to a 5% to 95% range (1% to 99% guaranteed). therefore, its v mod control range is 0.14 ? v set to 0.86 ? v set (approximately 0.14v to 0.86v). the ltc6992-3 and ltc6992-4 complete the family by providing one-sided clamping. the ltc6992-3 allows 0% to 95% duty cycle, and the ltc6992-4 allows 5% to 100% duty cycle. output polarity (pol bit) the duty cycle equation describes a proportional transfer function, where duty cycle increases as v mod increases. the ltc6992 includes a pol bit (determined by the divcode as described earlier) that inverts the output signal. this makes the duty cycle gain negative, reducing duty cycle as v mod increases. o pera t ion figure 3. pol bit functionality 6992 f03 out pol = 1 t out d ? t out out pol = 0 t out d ? t out d = v mod 0.8 ? v set ? 1 8 d = 1 ? v mod 0.8 ? v set ? 1 8 ? ? ? ? ? ?
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 17 69921234fc pol = 1 forces a simple logic inversion, so it changes the duty cycle range of the ltc6992-3 (making it 100% to 5%) and ltc6992-4 (making it 95% to 0%). these transfer functions are detailed in figure 4. table 2. duty cycle ranges part number duty cycle range vs v mod = 0v 1v pol = 0 pol = 1 ltc6992-1 0% to 100% 100% to 0% ltc6992-2 5% to 95% 95% to 5% ltc6992-3 0% to 95% 100% to 5% ltc6992-4 5% to 100% 95% to 0% o pera t ion figure 4. pwm transfer functions for all ltc6992 family parts v mod /v set (v/v) 0 duty cycle (%) 100 90 60 40 20 70 80 50 30 10 0 0.4 0.8 0.9 0.2 0.6 6992 f04a v mod /v set = 0.9 v mod /v set = 0.1 1 0.3 0.7 0.1 0.5 pol = 1 pol = 0 v mod /v set (v/v) 0 duty cycle (%) 100 90 60 40 20 70 80 50 30 10 0 0.4 0.8 0.9 0.2 0.6 6992 f04b 1 0.3 0.7 0.1 0.5 pol = 1 pol = 0 v mod /v set = 0.86 v mod /v set = 0.14 v mod /v set (v/v) 0 duty cycle (%) 100 90 60 40 20 70 80 50 30 10 0 0.4 0.8 0.9 0.2 0.6 6992 f02c 1 0.3 0.7 0.1 0.5 pol = 1 pol = 0 v mod /v set = 0.1 v mod /v set = 0.86 v mod /v set (v/v) 0 duty cycle (%) 100 90 60 40 20 70 80 50 30 10 0 0.4 0.8 0.9 0.2 0.6 6992 f02d 1 0.3 0.7 0.1 0.5 pol = 1 pol = 0 v mod /v set = 0.9 v mod /v set = 0.14 ltc6992-1 ltc6992-2 ltc6992-3 ltc6992-4
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 18 69921234fc changing divcode after start-up following start-up, the a/d converter will continue monitoring v div for changes. changes to divcode will be recognized slowly, as the ltc6992 places a priority on eliminating any wandering in the divcode. the typical delay depends on the difference between the old and new divcode settings and is proportional to the master oscillator period. t divcode = 16 ? (?divcode + 6) ? t master a change in divcode will not be recognized until it is stable, and will not pass through intermediate codes. a digital filter is used to guarantee the divcode has settled to a new value before making changes to the output. then the output will make a clean (glitchless) transition to the new divider setting. o pera t ion start-up time when power is first applied, the power-on reset (por) circuit will initiate the start-up time, t start . the out pin is held low during this time. the typical value for t start ranges from 0.5ms to 8ms depending on the master oscil- lator frequency (independent of n div ): t start(typ) = 500 ? t master the output will begin oscillating after t start . if pol = 0 the first pulse has the correct width. if pol = 1 (divcode 8), the first pulse width can be shorter or longer than expected, depending on the duty cycle setting, and will never be less than 25% of t out . during start-up, the div pin a/d converter must determine the correct divcode before the output is enabled. the start-up time may increase if the supply or div pin volt- ages are not stable. for this reason, it is recommended to minimize the capacitance on the div pin so it will properly track v + . less than 100pf will not affect performance. 6992 f06 out div stable v div v + t divcode t start 1st pulse width may be inaccurate figure 5. divcode change from 3 to 1 figure 6. start-up timing diagram div 0.5v/div out 1v/div v + = 3.3v r set = 200k v mod = 0.3v 100s/div 6992 f05 512s
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 19 69921234fc basic operation the simplest and most accurate method to program the ltc6992 is to use a single resistor, r set , between the set and gnd pins. the design procedure is a four step process. after choosing the proper ltc6992 version and pol bit setting, select the n div value and then calculate the value for the r set resistor. alternatively, linear technology offers the easy to use timerblox designer tool to quickly design any ltc6992 based circuit. download the free timerblox designer software at www.linear.com/timerblox. step 1: selecting the pol bit setting most applications will use pol = 0, resulting in a positive transfer function. however, some applications may require a negative transfer function, where increasing v mod re - duces the output duty cycle. for example, if the ltc6992 is used in a feedback loop, pol = 1 may be required to achieve negative feedback. step 2: selecting the ltc6992 version the difference between the ltc6992 versions is observed at the endpoints of the duty cycle control range. applications that require the output to never stop oscillating should use the ltc6992-2. on the other hand, if the output should be allowed to rest at gnd or v + (0% or 100% duty cycle), select the ltc6992-1. the ltc6992-3 and ltc6992-4 clamp the duty cycle at only one end of the control range, allowing the output to stop oscillating at the other extreme. if pol = 1 the clamp will swap from low duty cycle to high, or vice-versa. refer to table 2 and figure 4 for assistance in selecting the proper version. step 3: selecting the n div frequency divider value as explained earlier, the voltage on the div pin sets the divcode which determines both the pol bit and the n div value. for a given output frequency, n div should be selected to be within the following range. 62.5khz f out n div 1mhz f out (1a) a pplica t ions i n f or m a t ion to minimize supply current, choose the lowest n div value (generally recommended). for faster start-up or decreased jitter, choose a higher n div setting. alternatively, use table 1 as a guide to select the best n div value for the given ap- plication. with pol already chosen, this completes the selection of divcode. use table 1 to select the proper resistor divider or v div /v + ratio to apply to the div pin. step 4: calculate and select r set the final step is to calculate the correct value for r set using the following equation. r set = 1mhz ? 50k n div ? f out (1b) select the standard resistor value closest to the calculated value. example : design a pwm cir cuit that satisfies the following requirements: ? f out = 20khz ? positive v mod to duty cycle response ? output can reach 100% duty cycle, but not 0% ? minimum power consumption step 1: selecting the pol bit setting for positive transfer function (duty cycle increases with v mod ), choose pol = 0. step 2: selecting the ltc6992 version to limit the minimum duty cycle, but allow the maximum duty cycle to reach 100%, choose ltc6992-4. (note that if pol = 1 the ltc6992-3 would be the correct choice.) step 3: selecting the n div frequency divider value choose an n div value that meets the requirements of equation (1a). 3.125 n div 50 potential settings for n div include 4 and 16. n div = 4 is the best choice, as it minimizes supply current by us-
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 20 69921234fc applica t ions in f or m a t ion ing a large r set resistor. pol = 0 and n div = 4 requires divcode = 1. using table 1, choose the r1 and r2 values to program divcode = 1. step 4: select r set calculate the correct value for r set using equation (1b). r set = 1mhz ? 50k 4 ? 20khz = 625k since 625k is not available as a standard 1% resistor, substitute 619k if a 0.97% frequency shift is acceptable. otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. the completed design is shown in figure 7. 6992 f07 ltc6992-4 mod gnd set out v + div r1 976k divcode = 1 r2 102k r set 625k v mod 2.25v to 5.5v figure 7. 20khz pwm oscillator figure 8. duty cycle variation due to ?v set v mod (v) 0 duty cycle (%) 100 90 70 80 60 50 30 40 20 10 0 0.6 0.2 6992 f08 1 0.4 0.8 ?v set = 0mv ?v set = 30mv ?v set = ?30mv figure 9. fixed-frequency, arbitrary duty cycle oscillator 6992 f09 ltc6992-x mod gnd set out v + div r1 r2 r set2 r set1 2.25v to 5.5v d = 5 4 ? r set2 r set1 + r set2 ? 1 8 figure 8 demonstrates the worst-case impact of this varia- tion (if v set is at its 0.97v or 1.03v limits). this error is in addition to the inherent pwm duty cycle accuracy spec ? d (4.5%), so care should be taken if accuracy at high duty cycles (v mod near 0.9v) is critical. sensitivity to ? v set can be eliminated by making v mod proportional to v set . for example, figure 9 shows a simple circuit for generating an arbitrary duty cycle. the equation for duty cycle does not depend on v set at all. duty cycle sensitivity to ? v set the output duty cycle is proportional to the ratio of v mod / v set . since v set can vary up to 30mv from 1v it can effectively gain or attenuate v mod , as shown below when ? v set is added to the equation. d = v mod 0.8 ? v set + ? v set ( ) ? 1 8 for many designs, the absolute v mod to duty cycle accuracy is not critical. for others, making the simplifying assump- tion of ? v set = 0v creates the potential for additional duty cycle error, which increases with v mod , reaching a maximum of 3.4% if ? v set = C30mv. ? d ? ? v mod 800mv ? ? v set v set ? ? d ideal + 1 8 ? ? ? ? ? ? ? ? v set v set
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 21 69921234fc a pplica t ions i n f or m a t ion i set extremes (master oscillator frequency extremes) when operating with i set outside of the recommended 1.25a to 20a range, the master oscillator operates outside of the 62.5khz to 1mhz range in which it is most accurate. the oscillator will still function with reduced accuracy for i set < 1.25a. at approximately 500na, the oscillator output will be frozen in its current state. the output could halt in a high or low state. this avoids introducing short pulses while frequency modulating a very low frequency output. at the other extreme, it is not recommended to operate the master oscillator beyond 2mhz because the accuracy of the div pin adc will suffer. pulse width modulation bandwidth and settling time the ltc6992 has a wide pwm bandwith, making it suitable for a variety of feedback applications. figure 10 shows that the frequency response is flat for modulation frequencies up to nearly 1/10 of the output frequency. beyond that point, some peaking may occur (depending on n div and average duty cycle setting). duty cycle settling time depends on the master oscillator frequency. following a 80mv step change in v mod , the duty cycle takes approximately eight master clock cycles (8 ? t master ) to settle to within 1% of the final value. examples are shown in figures 11a and 11b. figure 10. pwm frequency response figure 11a. pwm settling time, 25% duty cycle figure 11b. pwm settling time, 50% duty cycle f mod /f out (hz/hz) 0.001 ?d(f mod )/?d(0hz) (db) 10 5 ?5 0 ?10 ?15 ?20 0.01 6992 f10 1 0.1 1, 50% 1, 80% 16 4, 50% 4, 15% v mod 0.1v/div out 2v/div duty cycle 5% div v + = 3.3v divcode = 0 r set = 200k v mod = 0.3v 40mv 10s/div 6992 f11a v mod 0.1v/div out 2v/div duty cycle 5% div v + = 3.3v divcode = 0 r set = 200k v mod = 0.5v 40mv 10s/div 6992 f11b
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 22 69921234fc power supply current the power supply current varies with frequency, supply voltage and output loading. it can be estimated under any condition using the following equation: ? if n div = 1 (divcode = 0 or 15): i s(typ) v + ? f out ? 39pf + c load ( ) ? + v + 320k + v + ? duty cycle r load + 2.2 ? i set + 85a if n div > 1 (divcode = 1 or 14): i s(typ) v + ? n div ? f out ? 27pf ? + v + ? f out ? 28pf + c load ( ) ? + v + 320k + v + ? duty cycle r load + 2.6 ? i set + 90a s upply b ypassing and pcb l ayout g uidelines the ltc6992 is a 2.4% accurate silicon oscillator when used in the appropriate manner . the part is simple to use and by following a few rules, the expected performance is easily achieved. adequate supply bypassing and proper pcb layout are important to ensure this. figure 14 shows example pcb layouts for both the tsot-23 and dfn packages using 0603 sized passive components. the layouts assume a two layer board with a ground plane layer beneath and around the ltc6992. these layouts are a guide and need not be followed exactly. applica t ions in f or m a t ion 1. connect the bypass capacitor, c1, directly to the v + and gnd pins using a low inductance path. the connection from c1 to the v + pin is easily done directly on the top layer. for the dfn package, c1s connection to gnd is also simply done on the top layer. for the tsot-23, out can be routed through the c1 pads to allow a good c1 gnd connection. if the pcb design rules do not allow that, c1s gnd connection can be accomplished through multiple vias to the ground plane. multiple vias for both the gnd pin connection to the ground plane and the c1 connection to the ground plane are recommended to minimize the inductance. capacitor c1 should be a 0.1f ceramic capacitor. 2. place all passive components on the top side of the board. this minimizes trace inductance. 3. place r set as close as possible to the set pin and make a direct, short connection. the set pin is a current summing node and currents injected into this pin directly modulate the operating frequency. having a short connection minimizes the exposure to signal pickup. 4. connect r set directly to the gnd pin. using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. use a ground trace to shield the set pin. this provides another layer of protection from radiated signals. 6. place r1 and r2 close to the div pin. a direct, short connection to the div pin minimizes the external signal coupling.
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 23 69921234fc typical a pplica t ions figure 14. supply bypassing and pcb layout constant on-time modulator 6992 ta02 ltc6992-1 mod gnd set out v + div r m2 9.31k r m1 1.05k r set 44.2k r in * 11.8k v ctrl v mod v set v in 0v to 2v r1 182k divcode = 2 (16, pol = 1) c1 0.1f out r2 976k v cc *optional resistor adjusts for desired v in range. as v in increases, t out increases and duty cycle decreases (because pol = 1) to maintain a constant t on . for constant off-time, just change divcode so pol = 0. if r m2 r m1 +r m2 = 0.9 then t on = n div ? 1.125s ? r set 50k applica t ions in f or m a t ion 6992 f14 ltc6992 mod gnd set out v + div c1 0.1f r1 r2 r set v + mod gnd set out v + div v + div set out gnd mod r1 r2 c1 r set v + c1 r1 r2 v + r set tsot-23 package dfn package
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 24 69921234fc t ypical applica t ions digitally controlled duty cycle with internal v ref reference variation eliminated programming n div using an 8-bit dac 6992 ta03 ltc6992-x mod gnd set out v + div r set ? + v + 1/2 ltc6078 r1 c1 0.1f r2 ltc1659 v out clk p cs/ld d in ref v cc gnd v + v + 0.1f 0.1f 6992 ta04 ltc6992-x mod gnd set out v + div r set c1 0.1f ltc2630-lz8 v out sck p cs/ld sdi v cc gnd 2.25v to 5.5v c2 0.1f divcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dac code 0 24 40 56 72 88 104 120 136 152 168 184 200 216 232 255 analog pwm duty cycle control (0v to 1v)
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 25 69921234fc t ypical applica t ions changing between two frequencies 6992 ta05 ltc6992-x mod gnd set out v + div r1 0.1f 0.1f r2 r set v + notes while this circuit is simpler than the circuit to the right, its frequency accuracy is worse due to the effect of v + supply variation from system to system and over temperature. notes 1. when the nmosfet is off, the frequency is set by r set = r set1 . 2. when the nmosfet is on, the frequency is set by r set = r set1 || r set2 . 3. v + supply variation is not a factor as the switching resistor is either floating or connected to ground. r vco v + ?hc04 f max f min analog pwm duty cycle control (0v to 1v) ltc6992-x mod gnd set out v + div r1 r2 r set1 r set2 v + analog pwm duty cycle control (0v to 1v) v + ?hc04 2n7002 f min f max simple diode temperature sensor 6992 ta06 ltc6992-2 mod gnd set out v + div r4 1000k moc207m q1 output d3 c1 1f r5 186k 5v 5v 0.1f 0.1f 5v lt6003 +10mv/c 5v r1 130k r2 50k r3 130k adjust for 50% duty cycle at 25c + ? r7 16.9k r8 84.5k r6 45.3k d1 1n458 r11 422 n div = 16 f = 10khz pwm output for isolated measurement +1% duty cycle change per degree c ?10c to 65c range with opto-isolator (dc: 15% to 95%) r9 365 0.1f
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 26 69921234fc motor speed/direction control for full h-bridge (locked anti-phase drive) t ypical applica t ions 6992 ta07 ltc6992-2 motor a1 a2 cw current flow v s 12v power h-bridge high = switch on mod gnd set out v + div r1 1000k 0.1f input 0v to 1v r2 280k v + r3 300k 2.6khz, 5% to 95% pwm 5% dc = clockwise 50% dc = stopped 95% dc = counter clockwise motor speed/direction control for full h-bridge (sign/magnitude drive) 6992 ta08 ltc6992-2 motor a3 a4 a5 cw current flow v s 12v power h-bridge high = switch on mod gnd set out v + div r4 1000k input 0v to 1v r5 280k v + r3 300k 2.6khz, 5% to 95% pwm 5% dc = slow 95% dc = fast direction h = ccw, l = cw 0.1f
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 27 69921234fc t ypical applica t ions ratiometric sensor to pulse width, non-inverting response 6992 ta09 ltc6992-1 c1 0.15f mod gnd set out v + div r1 1000k r2 186k v s output duty cycle = k ? 100% v s lt1490 k ? v s v s = 2.5v to 5.5v r set 316k + ? r3 10k k = 1 k = 0 r4 90.9k r5 10m r6 9.09k r sensor n div = 16 f out = 10khz 0.1f c2 0.22f 0.1f ratiometric sensor to pulse width, inverting response 6992 ta10 ltc6992-1 c1 0.15f mod gnd set out v + div r1 1000k r2 186k v s output duty cycle = (1Ck) ? 100% v s v s lt1490 v s = 2.5v to 5.5v r set 316k + ? r3 100k r4 10k k = 1 k = 0 r6 90.9k k ? v s r5 10k r6 9.09k r sensor n div = 16 f out = 10khz c2 0.22f 0.1f 0.1f
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 28 69921234fc t ypical applica t ions radio control servo pulse generator 6992 ta11 ltc6992-1 c1 1f mod gnd set out v + div r1 1000k r2 681k v s output 1ms to 2ms pulse every 16ms v s lt1490 v s = 2.5v to 5.5v r set 196k + ? r6 90.9k r5 130k r6 8.66k servo control pot 10k 2ms 1ms r6 9.09k n div = 4096 f out = 62.5hz, 16ms period c2 0.22f 0.1f 0.1f direct voltage controlled pwm dimming (0 to 15000 cd/m 2 intensity) 6992 ta12 ltc6992-1 mod gnd set out v + div f = 7.5khz n div = 64 5v d1 high intensity led ssl-lx5093xuwc r2 280k r set 105k v dimming r1 1m r3 90.9 c1 0.1f
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 29 69921234fc t ypical applica t ions wide range led dimming (0 to 85000 cd/m 2 brightness) 6992 ta13 ltc6992-4 mod gnd set out v + div r div1 1m r div2 280k 5v 5v lt6004 r set1 61.9k + ? 5v lt6004 + ? r3 10k v ref v fast r4 7.5k v dimming 0v to 1.65v v slow r2 7.5k r1 10k 5?100% n div = 64 f = 12.6khz 0?100% n div = 4096 f out = 100hz slow pwm controls 0 to 6000 cd/m 2 brightness fast pwm controls 6000 to 85000 cd/m 2 brightness c4 0.1f ltc6992-1 mod gnd set out v + div r div3 1m r div4 681k 5v 3.3v 5v r set2 124k c1 0.1f 3.3v in pv in pwm a1 d1 d2 lumileds lxhl-bw02 lt3518uf led + 0.1f
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 30 69921234fc isolated pwm (5% to 95%) controller 6992 ta14 ltc6992-2 mod gnd set out v + div lt1011 lt1636 concept design using simple r-c filtering for pwm control. not optimized for offsets. t1: pca epf8119s ethernet transformer r2 100k v + r10 499k + ? r15 10k 1khz source pwm r14 10k r1 10k 100khz intermediate pwm r9 20k l1 + ? c1 1f 0.1f l2 ltc6992-2 mod gnd set out v + div lt1011 lt1636 r4 10k isov + isov + isov + r11 787k r12 1m isopwm r13 280k r3 1k + ? r6 4.99k 1khz isolated pwm isolation barrier t1 r8 10k c3 1000pf r7 1k + ? c2 0.1f r17 10k r18 100k r16 100k ?? v + r5 20k c4 1f 0.1f 0.1f 0.1f 0.1f 0.1f t ypical applica t ions
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 31 69921234fc dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715 rev a) p ackage descrip t ion 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 0.10 (2 sides) 1 3 64 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb6) dfn 0405 0.25 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 45 chamfer 0.25 0.05 1.35 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.70 0.05 3.55 0.05 package outline 0.50 bsc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 32 69921234fc s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636 rev b) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 33 69921234fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 01/11 revised ja value for tsot package in the pin configuration. added note 7 for v oh and v ol in the electrical characteristics table. minor edit to the block diagram. minor edit to the equation in the duty cycle sensitivity to ?v set section. revised typical applications drawings. 2 4 12 19 25 b 07/11 revised description and order information sections added additional information to ?f out /?v + and included note 11 in electrical characteristics section added typical frequency error vs time curve to typical performance characteristics section added text to basic operation paragraph in applications information section corrected f out value in typical applications drawing 6692 ta13 1 to 3 3, 4 11 19 29 c 01/12 added mp-grade 1, 2, 3, 5
ltc6992-1/ltc6992-2/ ltc6992-3/ltc6992-4 34 69921234fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0112 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1799 1mhz to 33mhz thinsot silicon oscillator wide frequency range ltc6900 1mhz to 20mhz thinsot silicon oscillator low power, wide frequency range ltc6906/ltc6907 10khz to 1mhz or 40khz thinsot silicon oscillator micropower, i supply = 35a at 400khz ltc6930 fixed frequency oscillator, 32.768khz to 8.192mhz 0.09% accuracy, 110s start-up time, 105a at 32khz ltc6990 timerblox, voltage controlled oscillator frequency from 488hz to 1mhz, no caps, 2.2% accurate ltc6991 timerblox, very low frequency clock with reset cycle time from 2ms to 9.5 hours, no caps, 2.2% accurate ltc6993 timerblox, monostable pulse generator resistor set pulse width from 1s to 34sec, no caps, 3% accurate ltc6994 timerblox, delay block/debouncer resistor set delay from 1s to 34sec, no caps required, 3% accurate pwm controller for led driver 6992 ta15 ltc6992-1 mod gnd set out v + div 1m 681k 102k v in 8v to 16v analog pwm duty cycle control (0v to 1v) 5v lt3517 pwm tgen v ref ctrl sync fb isp isn tg shdn v in sw v c gndss r t c1 2.2f 0.1f r1 3.92m r2 124k 300ma c1 0.22f c2 4.7f c3 0.1f c4 0.1f r t 6.04k 2mhz d1 l1 6.8h lt3517 r sense 330m c1: kemet c0806c225k4rac c2: kemet c1206c475k3rac c3, c4: murata grm21br71h104ka01b c5: murata grm21br71h224ka01b d1: diode dfls160 l1: toko b992as-6r8n leds: luxeon i (white) m1: zetex zxmp6a13fta

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